
The SPI interface is the fastest interface of the Avisaro 2.0 module. It is designed to be connected to a micro controller or to programmable logic (FPGA). When connected to a micro controller we recommend to use the 'packet interface' (see details later), when connected to a FPGA, the simpler 'streaming modus' can be used. The SPI interface is not the default interface when shipped or when module was reseted to factory defaults.
The SPI bus timing is controlled by two parameters: clock polarity and clock phase. This is how those parameters effect bus timing:
| CPOL and CPHA settings | First data driven | Other data driven | Data sampled |
|---|---|---|---|
| CPOL = 0, CPHA = 0 | Prior to first SCK rising edge | SCK falling edge | SCK rising edge |
| CPOL = 0, CPHA = 1 | First SCK rising edge | SCK rising edge | SCK falling edge |
| CPOL = 1, CPHA = 0 | Prior to first SCK falling edge | SCK rising edge | SCK falling edge |
| CPOL = 1, CPHA = 1 | First SCK falling edge | SCK falling edge | SCK rising edge |
See the following timing diagrams for details (click to enlarge):
With each byte which is send to the Avisaro Module, one byte is also received (... which is true for all SPI interfaces). If there is no valid data to be send either direction, a hex 0xFF is send.
The SPI interface is designed to connect the Avisaro WLAN Module or Avisaro Logger Module to a Micro Controller.
See
here for a general describtion on how to configure Avisaro 2.0 products.
Use the following web site entries to control the SPI interface
Use the following command to control the spi interface
Once configured, one can send text commands or packet commands:
Use the following BASIC commands to control and access the SPI interface
The Script WR1 (
more) can also be used for SPI: