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Orientation ("PIN 1")

The Avisaro 2.0 module has 24 pins. Pin no 1 is in the top left corner, all other pin numbers counting counterclockwise. The orientation of the Base and Trailor module is shown in those diagrams.

  1. Base Module's pin 1 is marked by a triangle
  2. SD Trailor Module's pin 1 is in the top left corner. Hold module such that the slot opening points upwards.
  3. WLAN Trailor Module's pin 1 is in the top left corner. Hold module such that the antenna points upwards. 
20070920 Layout Blockschaltbild - 750
20070920 Layout Blockschaltbild sd - 750
20070920 Layout Blockschaltbild wlan - 750
20091127 Layout Blockschaltbild

RS232 (1x)

The RS232 interface is viewed as master or PC side. Thus, signals such as 'Ring' are inputs. There is no 'level shifter' onboard - all signals are TTL (3.3V) levels. Signals in brackets (such as GPIO(LED1)) show how pins are used in Avisaro Box or Avisaro Cube products.

No I/O

Name

  

Name

 I/O No
1 P

VBAT

20070920_Layout_Blockschaltbild_320

VCC (3.3V)

 P 24
2 O

GPIO (Red LED)

n.c.

 - 23
3 O

GPIO (Green LED)

n.c.

 - 22
4 I

GPIO (KEY)

n.c.

 - 21
5 I

DCD

n.c.

 - 20
6 I

DSR

n.c.

 - 19
7 O

DTR

n.c.

 - 18
8 I

RING

n.c.

 - 17
9 O

TXD

GPIO (open)

 - 16
10 I

RXD

GPIO (open)

 - 15
11 I

CTS

Reset

 I 14
12 O

RTS

GND

 P 13

'I/O': pin is input, output or power, 'n.c.': do not connect, leave open

RS232 (2x)

The RS232 interface is viewed as master or PC side. Thus, signals such as 'Ring' are inputs. There is no 'level shifter' onboard - all signals are TTL (3.3V) levels.

No I/O

Name

  

Name

 I/O No
1 P

VBAT

20070920_Layout_Blockschaltbild_320

VCC (3.3V)

 P 24
2 O

GPIO (LED1)

n.c.

 - 23
3 O

GPIO (LED2)

n.c.

 - 22
4 I

GPIO (KEY)

n.c.

 - 21
5 O

TXD-2

n.c.

 - 20
6 I

RXD-2

n.c.

 - 19
7 O

DTR-1

n.c.

 - 18
8 I

RING-1

n.c.

 - 17
9 O

TXD-1

GPIO

 I/O 16
10 I

RXD-1

GPIO

 I/O 15
11 I

CTS-1

Reset

 I 14
12 O

RTS-1

GND

 P 13

'I/O': pin is input, output or power, 'n.c.': do not connect, leave open

CAN (1x)

The CAN interface is operated as Rx and Tx. To connect the module to a CAN Bus, a transceiver circuitry is required to translate Rx/Tx into a CAN-H / CAN-L signal.

No I/O

Name

  

Name

 I/O No
1 P

VBAT

20070920_Layout_Blockschaltbild_320

VCC (3.3V)

 P 24
2 O

LED1

n.c.

 - 23
3 O

LED2

n.c.

 - 22
4 I

KEY

n.c.

 - 21
5 -

n.c.

n.c.

 - 20
6 -

n.c.

n.c.

 - 19
7 -

n.c.

n.c.

 - 18
8 -

n.c.

n.c.

 - 17
9 -

n.c.

n.c.

 - 16
10 -

n.c.

n.c.

 - 15
11 I

CAN Rx

Reset

 I 14
12 O

CAN Tx

GND

 P 13

'I/O': pin is input, output or power, 'n.c.': do not connect, leave open

CAN (2x)

Both CAN interface are operated as Rx and Tx. To connect the module to a CAN Bus, a transceiver circuitry is required to translate Rx/Tx into a CAN-H / CAN-L signal. Automotive CAN transceivers such as the TJA1041AT are supported. So are Single Wire CAN transceivers.

No I/O

Name

  

Name

 I/O No
1 P

VBAT

20070920_Layout_Blockschaltbild_320

VCC (3.3V)

 P 24
2 O

LED1

n.c.

 - 23
3 I

CAN 2 - Rx

n.c.

 - 22
4 O

CAN 2 - Tx

n.c.

 - 21
5 O

CAN - EN

n.c.

 - 20
6 O

CAN - STB

n.c.

 - 19
7 O

LED 2

n.c.

 - 18
8 I

KEY

n.c.

 - 17
9 -

n.c.

n.c.

 - 16
10 -

n.c.

n.c.

 - 15
11 I

CAN 1 Rx

Reset

 I 14
12 O

CAN 1 Tx

GND

 P 13

'I/O': pin is input, output or power, 'n.c.': do not connect, leave open

SPI (slave)

The SPI interface is implemented as a slave.

No I/O

Name

  

Name

 I/O No
1 P

VBAT

20070920_Layout_Blockschaltbild_320

VCC (3.3V)

 P 24
2 O

LED1

n.c.

 - 23
3 O

LED2

n.c.

 - 22
4 I

KEY

n.c.

 - 21
5 -

n.c.

n.c.

 - 20
6 -

n.c.

n.c.

 - 19
7 -

n.c.

n.c.

 - 18
8 -

n.c.

n.c.

 - 17
9 I

CS

n.c.

 - 16
10 O

MISO

n.c.

 - 15
11 I

MOSI

Reset

 I 14
12 I

SCK

GND

 P 13

'I/O': pin is input, output or power, 'n.c.': do not connect, leave open

The SPI bus is using 8 bit words.
Max SCK clock is 10 mHz.
The bus select (CS) is active low. It is recommended to deactivate the CS between data block in case clock glitches occured.

I2C (master or slave)

The I2C interface is implemented as a master or slave depending on configuration.

No I/O

Name

  

Name

 I/O No
1 P

VBAT

20070920_Layout_Blockschaltbild_320

VCC (3.3V)

 P 24
2 O

LED1

n.c.

 - 23
3 O

LED2

n.c.

 - 22
4 I

KEY

n.c.

 - 21
5 -

n.c.

n.c.

 - 20
6 -

n.c.

n.c.

 - 19
7 -

n.c.

n.c.

 - 18
8 -

n.c.

n.c.

 - 17
9 -

n.c.

SDA-0

 I/O 16
10 -

n.c.

SCL-0

 I/O  15
11 -

n.c.

Reset

 I 14
12 -

-

GND

 P 13

'I/O': pin is input, output or power, 'n.c.': do not connect, leave open

I/O, PWM, Analog Ports

If a pin is not used for data transmittion, this pin can be used as a input, output, pulse width modulation (PWM) or analog pin as described here:

No I/O

Name

  

Name

 I/O No
1 P

VBAT

20070920_Layout_Blockschaltbild_320

VCC (3.3V)

 P 24
2 I/O

GPIO

n.c.

 - 23
3 I/O

GPIO

n.c.

 - 22
4 I/O

GPIO

n.c.

 - 21
5 I/O

GPIO, PWM

n.c.

 - 20
6 I/O

GPIO, PWM

n.c.

 - 19
7 I/O

GPIO, PWM

n.c.

 - 18
8 I/O

GPIO, ADC

n.c.

 - 17
9 I/O

GPIO, PWM, ADC

I/O (open drain)

 I/O 16
10 I/O

GPIO, PWM

I/O (open drain)

 I  15
11 I/O 

GPIO, PWM

Reset

 I 14
12 I/O

GPIO 

GND

 P 13

'I/O': pin is input or output or pwm or analog input (ADC), 'p' power, 'n.c.': do not connect, leave open

Ethernet

The Ethernet interface is implemented using the ENC28J60 Ethernet controller by Microchip. This controller is connected to the Avisaro Module using the internal SPI interface. All drivers are allready in the Avisaro Firmware. The Avisaro Module has an 'auto-recovery' to detect if a ENC is connected. An example layout for an Ethernet extension can be found Mehr here.

No I/O

Name

  

Name

 I/O No
1 P

VBAT

20070920_Layout_Blockschaltbild_320

VCC (3.3V)

 P 24
2 O

LED1

n.c.

 - 23
3 O

LED2

n.c.

 - 22
4 I

KEY

SPI-CS

 - 21
5 -

n.c.

n.c.

 - 20
6 -

n.c.

SPI-SCK

 - 19
7 -

n.c.

SPI-MOSI

 - 18
8 -

n.c.

SPI-MISO

 - 17
9 -

n.c.

n.c.

 - 16
10 -

n.c.

n.c.

 - 15
11 -

n.c.

Reset

 I 14
12 -

-

GND

 P 13

'I/O': pin is input, output or power, 'n.c.': do not connect, leave open

JTAG Interface

For some projects, the JTAG interface to the processor might be required. The JTAG interface is accessible on the Base Module. Use test prods or similar to make contact. The JTAG interface is used in rare cases only, contact Avisaro is any questions arrise.

JTAG Interface